Bachelors Thesis

we will familiarize ourselves with both. We also give

We

Its designand implementation make up a large part of this work

Component I, Work Queue:

Background

for this

WQs provide the means to submit tasks to the deviceand will be described in more detail shortly. They are marked yellow in Figure 2.3.

toone of these

Therefore

and each group may onlyhave one attached

all information required to complete the operationare contained within [8, Sec. 3.2

Since the Linux Kernel version 5.10, a driver for the DSA has been available, whichcurrently lacks a counterpart on Windows Operating Systems [10, Sec. Installation]. Asa result, accessing the DSA is only possible under Linux

d which can be a single submission or a batch of given size. This can be seen in

, and the template parameter path electswhether to run on hardware (Intel DSA) or software (CPU).

juxtaposing

Firstly, there is the template parameter named path, and secondly, an additionalparameter int node. Both will be discussed in the following paragraphs.

s the performance of the DSA has been evaluated in great detail byReese Kuper et al. in [6], we will perform only a limited amount of benchmarks with thepurpose of determining behaviour in a multi-socket system, penalties from using IntelDML and throughput for transfers from DDR-SDRAM to HBM.

varies greatly, with batch operations leadingin throughput. Reese Kuper et al. observed that ‘SWQ observes lower throughputbetween 1 − 8 KB [transfer size]’ [6, pp. 6]. We however observe a much higher point ofequalization, pointing to additional delays introduced by programming the DSA throughIntel DML. Another limitation may be observed in this result, namely the inheren

in a very short amount of time,

This is apparently caused by I/Ofabric limitations [6, p. 5

the

lead

Megatransfers

Colleagues performed

when lack of free cache

Section

in to

henceforth

Consequently

We use the same methodology for the latter, requiring function pointersperforming dynamic memory management be passed

an instance of an object

in ‘multiple-writers’, in addition to the ‘read-after-write’ scenarios. However, due tothe constraints outlined in Section 4.1, the ‘multiple-writers’ scenario is prevented, byensuring that only one thread can perform the caching task for a given datum. Moreover,the requirement for user-provided memory management functions to be thread-safe(Section 4.1.1) ensures that two concurrent cache accesses will never receive the samememory region for their task. These two guarantees in conjunction secure the caches’integrity. Hence, the only relevant scenario is ‘read-after-write’, which is also accountedfor since the cache pointer is updated by CacheData::WaitOnCompletion only when alloperations have concluded. Situations where a caching task (read) depending on theresults of another task (write) are thereby prevented

Firstly, we delveinto the usage of locking and atomics to achieve thread safety. Finally, we apply thecache to Query-driven Prefetching, detailing the policies mentioned in Section 4.1.1 andpresenting solutions for the challenges encountered

ensures that two concurrent cache accesses will never receive the samememory region for their task.

For this reason, we intend to offload copy operations tothe DSA in this work,

implementation,which is why this chapter will extensively focus on the details of their implementation

to deadlock

Entry

caches

As a solution for this

We measure totaland per-pipeline duration and cache hit percentage for prefetching for 5 iterations with5 previous warm-up runs, and form the average

std::shared_ptr<T>

Entry

We measure totaland per-pipeline duration and cache hit percentage for prefetching for 5 iterations with5 previous warm-up runs, and form the average

As a solution for this

std::shared_ptr<T>

caches

implementation,which is why this chapter will extensively focus on the details of their implementation

to deadlock

Firstly, we delveinto the usage of locking and atomics to achieve thread safety. Finally, we apply thecache to Query-driven Prefetching, detailing the policies mentioned in Section 4.1.1 andpresenting solutions for the challenges encountered

For this reason, we intend to offload copy operations tothe DSA in this work,

in ‘multiple-writers’, in addition to the ‘read-after-write’ scenarios. However, due tothe constraints outlined in Section 4.1, the ‘multiple-writers’ scenario is prevented, byensuring that only one thread can perform the caching task for a given datum. Moreover,the requirement for user-provided memory management functions to be thread-safe(Section 4.1.1) ensures that two concurrent cache accesses will never receive the samememory region for their task. These two guarantees in conjunction secure the caches’integrity. Hence, the only relevant scenario is ‘read-after-write’, which is also accountedfor since the cache pointer is updated by CacheData::WaitOnCompletion only when alloperations have concluded. Situations where a caching task (read) depending on theresults of another task (write) are thereby prevented

ensures that two concurrent cache accesses will never receive the samememory region for their task.

Consequently

We use the same methodology for the latter, requiring function pointersperforming dynamic memory management be passed

an instance of an object

henceforth

when lack of free cache

in to

lead

Section

Colleagues performed

Megatransfers

the

This is apparently caused by I/Ofabric limitations [6, p. 5

varies greatly, with batch operations leadingin throughput. Reese Kuper et al. observed that ‘SWQ observes lower throughputbetween 1 − 8 KB [transfer size]’ [6, pp. 6]. We however observe a much higher point ofequalization, pointing to additional delays introduced by programming the DSA throughIntel DML. Another limitation may be observed in this result, namely the inheren

juxtaposing

d which can be a single submission or a batch of given size. This can be seen in

in a very short amount of time,

s the performance of the DSA has been evaluated in great detail byReese Kuper et al. in [6], we will perform only a limited amount of benchmarks with thepurpose of determining behaviour in a multi-socket system, penalties from using IntelDML and throughput for transfers from DDR-SDRAM to HBM.

Firstly, there is the template parameter named path, and secondly, an additionalparameter int node. Both will be discussed in the following paragraphs.

, and the template parameter path electswhether to run on hardware (Intel DSA) or software (CPU).

Since the Linux Kernel version 5.10, a driver for the DSA has been available, whichcurrently lacks a counterpart on Windows Operating Systems [10, Sec. Installation]. Asa result, accessing the DSA is only possible under Linux

all information required to complete the operationare contained within [8, Sec. 3.2

and each group may onlyhave one attached

toone of these

WQs provide the means to submit tasks to the deviceand will be described in more detail shortly. They are marked yellow in Figure 2.3.

Component I, Work Queue:

Therefore

we will familiarize ourselves with both. We also give

for this

Background

Its designand implementation make up a large part of this work

We

Bachelors Thesis