Bit line
two stable states, bi-state
Bit line
two stable states, bi-state
b
this b is different b than the b in the next line nonblocking assignment is taking a snapshot of a,b,c and then write to a,b,c
Q
On a knife edge, the D will copy its value to Q
ROM = 1
011-
ROM
IO = 1
0101 IO
VIDEO = 1
000- VIDEO
RAM = 1;
1--- RAM
z = a - b;
you can write to a variable twice
take precedence
z = a + b;
take precedence
z = 4’b0;
default value
blockingassignment”:use in always_com
the normal equal assignment
n1(a, b, abn),n1: A mynand2connected to a, b, and abnn2(a, abn, aa),n3(abn, b, bb),n4(aa, bb, y)
instances of a variable
module mynand2(input logic a, b,output logic y);assign y = ~(a & b);endmodule
module for mynand2:n4
a & b
division and modulus are actuallly four AND gates
multiply is ??
Divide
very hard to do in hardware, so avoid
y = s ? d1 : d0;endmoduley~001d0[3..0]y~101y~201sd1[3..0] y[3..0]y~301
when s =1 , y = d1, and y=d0 when s=0
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this is &a