Features• VCE = 650 V• IC = 40 A• Powerful monolithic diode optimized for ZCS applications• High ruggedness, temperature stable behavior• Very low VCEsat and low Eoff• Easy paralleling capability due to positive temperature coefficient in VCEsat• Low EMI• Low electrical parameters depending (dependence) on temperature• Qualified according to JESD-022 for target applications• Pb-free lead plating; RoHS compliant• Complete product spectrum and PSpice Models: http://www.infineon.com/igbt/

Current Loop Feedback Configuration(Sizing of the Current Transformer Turns Ratio and Sense Resistor (RS)

Similar to other power management devices, whenlaying out the PCB it is important to use star grounding techniques and to keep filter and high frequency bypasscapacitors as close to device pins and ground as possible. To minimize the possibility of interference caused bymagnetic coupling from the boost inductor, the device should be located at least 1 inch away from the boostinductor. TI recommends the device not be placed underneath magnetic elements

The bridge rectifier must be rated to carry the full line current. The voltage rating of the bridge should be at least600 V. The bridge rectifier also carries the full inrush current as the bulk capacitor COUT charges when line isconnected.

Detailed Design Procedure

A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT,provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. TIrecommends a load of less than 0.5 mA, but if the resistance on PKLMT is very high, TI recommends a smallfilter capacitor on PKLMT to avoid operational problems in high-noise environments.

One of the main benefits from the 180° interleaving of phases is significant reductions in the high-frequencyripple components of both the input current and the current into the output capacitor of the PFC preregulator.Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases theburden of filtering conducted-EMI noise and helps reduce the EMI filter and CIN sizes. Additionally, reduced high-frequency ripple current into the PFC output capacitor, COUT, helps to reduce its size and cost. Furthermore, withreduced ripple and average current in each phase, the boost inductor size can be smaller than in a single-phasedesign

The UCC28070 power factor corrector IC controls two CCM (Continuous Conduction Mode) Boost PFC powerstages operating 180° out of phase with each other. This interleaving action reduces the input and output ripplecurrents so that less EMI filtering is needed and allows operation at higher power levels than a non-interleavedsolution.

RSYN RSYNTH resistance 15 750 kΩRRDM RDM resistance 30 330 kΩ

Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the soft-start slew ratebased on an internally-fixed, 10-μA current source. The regulation reference voltage for VSENSE is clamped toVSS until VSS exceeds 3 V. Upon recovery from certain fault conditions, a 1-mA current source is present at theSS pin until the SS voltage equals the VSENSE voltage. Pulling the SS pin below 0.6 V immediately disablesboth GDA and GDB outputs.